System circuits like chips, integrated circuits (ICs) and system-on-chip (SOC) have become the key hardware components in modern information society. Generally speaking, a chip has a core circuit and an I/O circuit. The core circuit implements main functions of the chip, e.g., logic operations, signal processing/conversion, coding/decoding and data management. The I/O circuit handles input/output signal exchange with external circuits through pins and pads of the chip, such that the core circuit can communicate with external circuits. Because the I/O circuit directly interfaces external environment (external circuits), the I/O circuit must has a certain level of tolerance for variety of external environments.
Please refer to FIG. 1. FIG. 1 illustrates a prior art I/O circuit 10 in a system circuit S0. The system circuit S0 can be a chip, and an internal circuit 12 can be a core circuit of the chip or a pre-driver for signal outputting. The I/O circuit 10 includes a buffer 18 for driving output signal. The buffer 18 is set between the internal circuit 12 and an I/O port (labeled as I/O in FIG. 1), where the I/O port is a pad (pin) of the chip. The information outputted by the internal circuit 12 can be transmitted to the I/O circuit 10 in the form of the input signals IP and IN (which are usually a pair of differential signals), then the buffer 18 can drive an output signal DP at the I/O port according to the input signals IP, IN; and thus information of the internal circuit 12 can be outputted.
Since the I/O port directly interfaces external environment (e.g., a printed circuit board or another chip), signal level at the I/O port is easily affected by external environment. For example, over-voltage may happen at the I/O port. That is, because of unexpected short-circuit or other reasons, voltage level at the I/O port may rise abnormally, even rise above the operation bias voltage of the I/O circuit 12. To reduce affection of over-voltage, the buffer 18 has an additional stacked transistor Mc, and the I/O circuit 10 also includes an n-well pull-up circuit 16 and a gate tracking circuit 14 for over-voltage protection. The n-well pull-up circuit 16 connects to the I/O port for responding over-voltage by providing a signal VNW and a gate signal GT according to voltage at the I/O port. The gate tracking circuit 14 connects between the internal circuit 12 and the buffer 18 for controlling electrical connection between the internal circuit 12 and the buffer 18.
As shown in FIG. 1, the buffer 18, the gate tracking circuit 14 and the n-well pull-up circuit 16 of the I/O circuit 10 are biased between operation bias voltages VCCA (a positive voltage) and GNDA (ground). The buffer 18 has two transistors Md1, Md2 and the stacked transistor Mc. The transistors Md1, Md2 drive the output signal DP at the I/O port, and the stacked transistor Mc locates between the transistors Md1, Md2. Note that the bulk of the transistor Md1 is biased by the signal VNW. The n-well pull-up circuit 16 includes transistors Ma1-Ma3; the gate tracking circuit 14 has transistors Mb1, Mb2 forming a transmission gate and another transistor Mb3. The bulk of the transistor Mb2 and the source of the transistor Mb3 are also biased by the signal VNW. That is, the three p-channel transistors Md1, Mb2 and Mb3 have their n-well bulks biased by the signal VNW.
Normal operation (when over-voltage does not happen) of the internal circuit 12 and the I/O circuit 10 can be described as follows. In normal operation, signal level at the I/O port should be alternating between the operation bias voltages VCCA and GNDA. Then, in the n-well pull-up circuit 16, the transistors Ma2, Ma3 are off (with their gates biased at voltage VCCA), the gate signal GT remains a low level (close to voltage GNDA), and the transistor Ma1 is on to keep the signal VNW high (close to voltage VCCA). In the gate tracking circuit 14, voltage at the node Np1 should also alternate between the operation bias voltages VCCA and GNDA, so the transistor Mb3 is off (with it gate biased at voltage VCCA), the transistor Mb1 is on and the transistor Mb2 is also on (with its gate biased by the low gate signal GT), so the node Np2 can be conducted to the node Np1 allowing the signal IP (from the internal circuit 12) to be transmitted to the buffer 18 for normal signal outputting.
On the other hand, when over-voltage occurs at the I/O port, the voltage level at the I/O port rise above the operation bias voltage VCCA; for example, the operation bias voltage VCCA is 3.3V, and voltage level at the I/O port may rise to 5V because of unexpected external environment change (like short-circuit). Under over-voltage circumstance, because the voltage level at the I/O port (i.e., level of the signal DP) rises above the voltage VCCA, the transistors Ma2, Ma3 in the n-well pull-up circuit 16 start to turn on. The turned-on transistor Ma3 makes the signal GT rise close to the over-voltage level of the signal DP, and also turns off the transistor Ma1. Similarly, the turned-on transistor Ma2 pulls the signal VNW close to the over-voltage level of the signal DP.
In the buffer 18, the voltage levels at the node Np3 and the bulk of the transistor Md1 both rise close to the over-voltage signal DP, so the transistor Md1 is off. The transistor Mc is on such that the node Np4 has a level close to a voltage (VCCA−Vth_Mc), where Vth_Mc is threshold voltage of the transistor Mc. In this way, over-voltage at the node Np3 will not directed feed into the node Np4, and then the transistor Md2 is protected.
In the gate tracking circuit 14, the transistor Mb3 turns on with its source signal VNW rising above the operation bias voltage VCCA due to over-voltage and the voltage level at the node Np1 is pulled close to the over-voltage level of the signal DP. For the transistor Mb2, over-voltage levels at its gate (biased by the signal GT), its bulk (biased by the signal VNW) and the node Np1 make the transistor Mb2 off. In this way, over-voltage will not damage the internal circuit 12 through the node Np2.
However, the prior art I/O circuit 10 in FIG. 1 has some disadvantages while performing over-voltage protection. For example, when over-voltage happens, reliability of the transistor Mb2 can be damaged. As described above, during over-voltage event, the transistor Mb2 has over-voltage at its gate (biased by the gate signal GT), its bulk (biased by the signal VNW) and the node Np1. At this time, if the internal circuit 12 happens to send a low IP signal to the node Np2, gate oxide of the transistor Mb2 will suffer a great voltage difference across the node Np2 (with a low level voltage) and the gate (with an over-voltage signal GT). This over-voltage voltage difference usually can reach a level close to breakdown voltage of the gate oxide of the transistor Mb2, and thus make the transistor Mb2 vulnerable. The aforementioned reliability concern also addresses anther disadvantage of the prior art: the prior art over-voltage protection technique can not inform the internal circuit 12 of incoming over-voltage, leaving no room for the internal circuit 12 to properly response the over-voltage events.